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          Mirror operated in collaboration with local support

          Hardware Architecture

          Authors and titles for recent submissions

          [ total of 7 entries: 1-7 ]
          [ showing up to 25 entries per page: fewer | more ]

          Thu, 21 May 2020

          [1]  arXiv:2005.09748 [pdf, other]
          Title: The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework
          Subjects: Hardware Architecture (cs.AR)

          Wed, 20 May 2020

          [2]  arXiv:2005.09526 (cross-list from eess.SP) [pdf, other]
          Title: In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications
          Subjects: Signal Processing (eess.SP); Hardware Architecture (cs.AR); Machine Learning (cs.LG); Neural and Evolutionary Computing (cs.NE)

          Tue, 19 May 2020

          [3]  arXiv:2005.08478 [pdf, other]
          Title: Energy-Efficient On-Chip Networks through Profiled Hybrid Switching
          Comments: To appear in the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI'20), Beijing, China
          Subjects: Hardware Architecture (cs.AR)
          [4]  arXiv:2005.08183 (cross-list from cs.CR) [pdf, other]
          Title: A Lightweight Isolation Mechanism for Secure Branch Predictors
          Comments: 13 pages, 10 figures, submitted to MICRO 2020
          Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)
          [5]  arXiv:2005.08098 (cross-list from cs.DC) [pdf, other]
          Title: Systolic Tensor Array: An Efficient Structured-Sparse GEMM Accelerator for Mobile CNN Inference
          Comments: Accepted by IEEE Computer Architecture Letters on 3/4/2020
          Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR); Machine Learning (cs.LG); Signal Processing (eess.SP)

          Mon, 18 May 2020

          [6]  arXiv:2005.07613 [pdf, other]
          Title: SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors
          Comments: To appear at ISCA 2020
          Subjects: Hardware Architecture (cs.AR)

          Fri, 15 May 2020

          [7]  arXiv:2005.07137 (cross-list from eess.SP) [pdf, other]
          Title: ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator
          Subjects: Signal Processing (eess.SP); Hardware Architecture (cs.AR)
          [ total of 7 entries: 1-7 ]
          [ showing up to 25 entries per page: fewer | more ]
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